1. Field of the Invention
The present invention relates to a packet data communication on-chip interconnect system, and more particularly, to a network interface efficiently controlling transaction performed between at least one master intellectual property (IP) block and at least one slave IP block connected via a Network on a Chip (NoC), and a packet data communication on-chip interconnect system including the network interface.
2. Description of the Related Art
An Advanced Microcontroller Bus Architecture (AMBA) Advanced extensible Interface (AXI) protocol is a more suitable bus protocol for a high-speed/high-end system than a related art on-chip bus protocol and has channels associated with read, write, address, and write response, which are respectively separated, individually operated, and have transaction properties such as multiple-outstanding address, write data interleaving.
An NoC is a network style on-chip interconnect system manufactured to overcome structural defects of a related art bus structural on-chip interconnect system. A high-speed/high-end/low power System on a Chip (SoC) may be embodied via the NoC. According to a packet data communication mode defined to support an AXI protocol in the NoC 100, a plurality of Intellectual Property (IP) blocks 110 shown in FIG. 1 may perform efficient data processing via packet routing of an NoC backbone 120.
In designing a packet data communication on-chip interconnect system shown in FIG. 1, a system designer may variously design the blocks 110 or the NoC backbone 120 according to the AXI protocol. The AXI protocol may be easily applied to any field such as not only a point-to-point system but also a multilayer system, via an interface between at least one master IP block and at least one slave IP block. Particularly, since the AXI protocol supports multi-transaction elegantly, parallel burst transmission is possible, thereby improving throughput. Therefore, a particular operation may be performed for a short time and various operations are performed by a plurality of IP blocks integrated in one chip, thereby reducing power consumption.
According to the AXI protocol, a master IP block is cross connected to a slave IP block via a network interface, when a lock operation is performed between one master IP block and the slave IP block, an arbiter in an interconnect system may control a transaction input from another master IP block to the slave IP block until an unlock transfer is issued from the master IP block requesting a lock access. However, in a packet data communication on-chip interconnect system, since a master IP block is connected to an NoC backbone via a network interface and is connected to a destination slave IP block via at least one router included in the NoC backbone, there is no centralized data transfer controller between the master IP block and the slave IP block.
As described above, since the centralized data transfer controller does not exist in the packet data communication on-chip interconnect system, when the packet data communication interconnect system supports a lock operation defined by the AXI protocol, problems described below may occur.
When a lock sequence is transferred from a second master IP block to a slave IP block while a transaction is performed between a first master IP block and the slave IP block, according to the AXI protocol, a lock access requested by the second master IP block may not be accepted. In this case, the second master IP block has to wait for a ready response with respect to the lock access for a predetermined amount of time or has to retransfer the lock sequence when the ready response is not received, thereby generating a delay in processing a certain task and dropping a traffic efficiency of an NoC backbone.
When a transaction including a lock sequence is input from a second master IP block to a slave IP block while a lock operation is performed between a first master IP block and the slave IP block, according to the AXI protocol, the lock operation performed between the first master IP block and the slave IP block fails. In this case, the slave IP block has to transfer a SLVERR response with respect to the lock sequence to the first master IP block and the first master IP block has to retransfer the lock sequence to the slave IP block to perform the lock operation from the beginning again. Therefore, with an increase of traffic of an NoC backbone, efficiency of utilizing a resource of the first master IP block may be decreased.